The internal routing, Chip will function as a mini “Internets”
April 15, 2012
Internet, Technology
Computer chips stopped getting faster. To continually increase computing power chips’ at a level that we are used to, chip manufacturers will even give them extra “cores,” or processing units. Today, a typical chip may have six or eight cores, all communicating with each other through a package of cable, called the bus. However, by bus, only a couple of core talk at a time, which would be a severe limitation on the chips with hundreds or even thousands of cores, an electrical engineer many see as The future of computing.
Wants Li-Shiuan Peh, a professor of electrical engineering and computer science at MIT, to communicate the core in the same way a computer connected to the Internet to do: “. Package “The bundling of information they send core router each with its own, Which sends the packet to be one of several paths, depending on network conditions overall.
In principle, multicore chips are faster than single-core chip because they can share the computing tasks and run on multiple cores simultaneously. Core working on the same task over to share data, but to date, the number of cores on a commercial chip has a low enough of a communication bus is able to handle the extra load. That changed, however: “The bus reached the border,” said Peh. “They use a size eight core.” The 10-core chip found in high-end servers tend to add a second bus, but this approach will not work for chips with hundreds of hundreds of cores.
For one thing, Peh said, “The bus took a lot of power, because they are trying to push the cable length to eight or 10 cores at the same time.” This kind of network Peh proposing, on the other hand, core Each communicates only four core near it. “Here, you’re driving a short segment of cable, allowing you to go lower voltage,” he explained.
In on-chip network, however, the data packets travel from one major to another must stop every router in between. In addition, if two packets arrive the router at the same time, one of them must be stored in memory while the other holds the router. Many engineers, Peh said, worried that the additional requirements would introduce considerable delay and computational complexity to offset the advantage of packet transfer. “The biggest problem, I think, is that the industry now, people do not know how to build these networks, because the bus has for decades,” said Peh.
Peh and his colleagues developed two strategies to overcome this problem. One of them is something they call “virtual past.” On the Internet, when a packet arrives at a router, check the router address information before deciding which way to send it. With a virtual pass, however, each router sends the signal to the front face, so it can be preset to switch, accelerate the package without further calculations. In the group of test chip, Peh said virtual pass allowed close approach to the maximum data transmission rate predicted by theoretical studies.
Another approach is something called a low signal swing. Digital data consisting of ones and zeros, are transmitted through communication channels as high and low voltage. Of Sunghyun Park, a PhD student advised by both Peh and Anantha Chandrakasan, an F. Joseph and Nancy P. Keithley Professor of Electrical Engineering, developed a circuit that reduces the voltage swing between high and low of a volt to 300 millivolts. With the combination of the signal passing through the virtual and low-swing, chip test the researchers’ energy consumption is 38 percent lower than the previous test chip packet-switched. The researchers have work to do, said Peh, before Chip test power consumption as they got close to the theoretical limit of the rate of data transmission is not. But, he added, “if we compare it to the bus, we get an order of magnitude savings.”